Riviera is a powerful, high performance ASIC and High Density FPGA verification environment. Riviera is optimized for long simulation runs and currently supports the Unix, Linux and Windows NT operating systems. The environment is modular and all tools can be used as stand-alone applications or as one integrated solution. The product includes:
VHDL / Verilog / Mixed simulation engine
Libraries and source files management system
Design Profiler / HDL Optimizer
Advanced Debugging Tools
Graphical User Interface (GUI)
Additionally, Riviera provides both batch mode or graphical user interface (GUI) operation for compilation, simulation, library and source files management to facilitate extensive regression testing of ASIC and High Density FPGA designs.
All Riviera programs can be controlled exclusively from the command line, which is especially useful for automatic project verification. In addition, the simulator includes an interpreter of commands that are used to control the simulation and the entire environment.
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