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Cadence Allegro and OrCAD 17.20.000-2016 HF033 x64 €80 buy download


Cadence Design Systems, Inc. has released an update (HF033) to OrCAD Capture, PSpice Designer and PCB Designer 17.20.000-2016. This latest release reduces PCB development time by addressing the need to design reliable circuits for smaller, more compact devices.

Fixed CCRs: SPB 17.20.000-2016 HF033
1828672 ADW ADWSERVER LDAP connection error while trying to log in to DBeditor
1840699 ADW DBEDITOR Unable to release footprint model due to older version being linked to a DE-HDL Block Model
1852402 ALLEGRO_EDITOR DATABASE Cutouts are not converted correctly when opening release 16.6 board in release 17.2-2016
1855223 ALLEGRO_EDITOR DATABASE Release 16.6. BoardOutline not fully converted to release 17.2-2016 Cutout Layer
1855252 ALLEGRO_EDITOR DATABASE Unable to open a previously saved release 17.2-2016 database
1863025 ALLEGRO_EDITOR DRC_CONSTR Shape voiding to Via pad with backdrill keepout is oversizing the Dynamic shape void by the backdrill keepout
1854087 ALLEGRO_EDITOR EDIT_ETCH Sliding arc crashes PCB Editor
1840667 ALLEGRO_EDITOR INTERACTIV Choosing 'Change Text block to' from pop-up displays message 'E- (SPMHGE-150): Text font is not defined'
1849133 ALLEGRO_EDITOR INTERACTIV On choosing 'Change Text block to' on text , 'Text font is not defined' message appears
1854695 ALLEGRO_EDITOR MANUFACT PCB Editor crashes while performing nc_route
1854634 ALLEGRO_EDITOR NC NC Drill file is generated with half the number of Drill Holes on enabling 'Optimize drill head travel'
1856773 ALLEGRO_EDITOR NC Issue with Optimize Drill head travel in hotfix 031: Missing drill holes
1860876 ALLEGRO_EDITOR NC NC route critical difference between hotfix 031 and 022: No slots found warning
1758671 ALLEGRO_EDITOR OTHER Export parameters takes long time to export and some times the process hangs
1040989 ALLEGRO_EDITOR SHAPE PCB Editor crashes while editing board outline
1328385 ALLEGRO_EDITOR SHAPE Check for missing thermal reliefs when shapes overlap
1366376 ALLEGRO_EDITOR SHAPE Thermal created for Xhatch shape overlapping another shape, but not created when solid shapes overlap
1716436 ALLEGRO_EDITOR SHAPE Acute angle trim should not violate DRC.
1822377 ALLEGRO_EDITOR SHAPE Setting shape parameter Acute angle trim control to Full round produces unwanted shape to keepout DRCs
1826436 ALLEGRO_EDITOR SHAPE Same net shape to hole spacing not voiding shape for cline of different net moved close to vias of same net shapes
1834510 ALLEGRO_EDITOR SHAPE Same Net Shape to Via Spacing does not always clear correctly
1850716 ALLEGRO_EDITOR SHAPE 'DiffPair combined void for vias added with Return Path option' does not work with fillet and pad suppression
1852814 ALLEGRO_EDITOR SHAPE Thermal reliefs are not created after placing modules.
1853453 ALLEGRO_EDITOR SHAPE Route keepout clipping of cross-hatched shapes needs to be corrected
1859391 ALLEGRO_EDITOR SHAPE Shapes are not using 'minimum aperture for gap width' for voiding after back drill update.
1859410 ALLEGRO_EDITOR SHAPE Shape to Teardrop is not using same net spacing rules
1825397 ALLEGRO_EDITOR UI_FORMS Option panel disappears in release 17.2-2016
1854070 ALLEGRO_EDITOR UI_GENERAL enable_command_window_history prevents many aliases and commands from working correctly
1855180 ALLEGRO_EDITOR UI_GENERAL Comma and dot do not work in funckey if 'enable_command_window_history' is set
1860003 ALLEGRO_EDITOR UI_GENERAL Icons and features missing or behaving differently in release 17.2-2016, Hotfix 031
1861278 ALLEGRO_EDITOR UI_GENERAL Icons and menus missing in PCB Editor in release 17.2-2016, Hotfix 031
1862292 ALLEGRO_EDITOR UI_GENERAL Layout Pins icon missing in toolbar in Symbol Editor since Hotfix 031
1793284 ALLEGRO_PROD_TOOLB CORE Limit View (V1R, V2R, COM) for OUTLINE layer.
1712701 ALTM_TRANSLATOR CAPTURE Third-party translator shows error for missing operand
1802182 ALTM_TRANSLATOR CAPTURE Imported schematic has connectivity loss
1802462 ALTM_TRANSLATOR CAPTURE Hierarchical ports placed incorrectly for imported third-party design
1823935 ALTM_TRANSLATOR CAPTURE Translating third-party schematics with hierarchical pages from Design Entry CIS
1830570 ALTM_TRANSLATOR CAPTURE Third-party to Capture translation is translating only one page out of 32
1839627 ALTM_TRANSLATOR CAPTURE Third-party translator is not importing complete schematic
1846965 ALTM_TRANSLATOR CAPTURE Cannot translate third-party schematic
1816767 ALTM_TRANSLATOR DE_HDL Error when translating third-party schematic to DE-HDL
1845601 ALTM_TRANSLATOR PCB_EDITOR Cannot operate third-party PCB translation in release 17.2-2016 Allegro Venture PCB Designer license
1841060 APD DIE_GENERATOR Cannot 'die text out' from SiP Layout or Allegro Package Designer
1793232 APD SHAPE When fillet/taper not connected to a pin, voiding process incorrectly applies shape clearance values
1846541 APD SHAPE shape degassing does not obey void to shape boundary
1863446 ASDA CONSTRAINT_MA A space in the name of a spacing or physical constraint results in the incorrect constraint set name
1859678 ASDA VARIANT_MANAG SDA - When hovering over all three buttons, under Preferred Parts in the Variant info it says (Do not install)
1815839 CONCEPT_HDL CORE Allegro Design Entry HDL crashes when entering Location data manually
1841857 CONCEPT_HDL CORE Unable to modify Components in non-windows mode
1852096 CONCEPT_HDL CORE Creating a block using top-down approach does not generate the CSB file
1857390 CONCEPT_HDL CORE DE-HDL crashes on moving symbol
1789070 CONCEPT_HDL OTHER Having folder 'allegro' in cpm root directory gives error while launching layout editor from Project Manager
1862484 CONSTRAINT_MGR CONCEPT_HDL Extracting an ECSet in SigXP is missing a t-point
1863045 CONSTRAINT_MGR CONCEPT_HDL Pin pairs deleted for a few differential pairs after upreving the design to release 17.2-2016
1863054 CONSTRAINT_MGR CONCEPT_HDL Differential Pairs are treated as invalid objects on upreved design
1863094 CONSTRAINT_MGR CONCEPT_HDL Pin-Pairs are shown duplicated in the topology for the extracted object (Diff Pair)
1831998 CONSTRAINT_MGR OTHER 'Tools - Options' settings not saved on closing Constraint Manager
1855324 CONSTRAINT_MGR OTHER Enable the option 'Expand Hierarchy' in 'Find and Replace' dialog, by default
1860847 CONSTRAINT_MGR OTHER 'Include Routed interconnect' option once enabled, should remain enabled for that board file
1843359 EAGLE_TRANSLATOR PCB_EDITOR While importing third-party PCB, many footprints do not convert, even though the log file says footprint created
1839978 SCM REPORTS dsreportgen unable to output reference designator from a lower-level hierarchical block if it has a single component
1850013 SIP_LAYOUT OTHER Environment variable 'icp_disable_cte_auto_update' needs grammatical change
1833742 SIP_LAYOUT PADSTACK_EDIT When creating Die to Die Via using Generate Padstacks, resultant pad stack has wrong Layers
1619098 SIP_LAYOUT SHAPE Acute angle of shape in design
1728628 SIP_LAYOUT SHAPE Auto-void in dynamic shape does not disappear if object is removed
1854592 SIP_LAYOUT VIA_STRUCTURE Create via structure returns an error

About Allegro and OrCAD 17.2-2016. The OrCAD 17.2-2016 release introduced new capabilities for OrCAD Capture, PSpice Designer, and PCB Designer 17.2-2016 that address challenges with flex and rigid-flex design as well as mixed-signal simulation complexities in IoT, wearables, and wireless mobile devices. This latest release reduces PCB development time by addressing the need to design reliable circuits for smaller, more compact devices.
- OrCAD Flex and Rigid-Flex Technologies
To enable a faster and more efficient flex and rigid-flex design creation critical to IoT, wearables and wireless devices, the OrCAD 17.2-2016 portfolio enables several new capabilities for flex and rigid flex design to minimize design iterations. Key flex and rigid flex features include: Stack-up by zone for flex and rigid-flex designs, Inter-layer checks for rigid-flex designs, Contour and arc-aware routing.
- New Cross-Section Editor
In the OrCAD PCB Designer 17.2-2016 release, the Cross-Section Editor has been redesigned to leverage the underlying spreadsheet technology found in the Constraint Manager. It offers a one-stop shop for features that require the cross section for their setup, such as dynamic unused pad suppression and embedded component design. The Cross-Section Editor has been enhanced to support multiple stackups for rigid-flex design, each capable of supporting conductor and non-conductor layers such as Soldermask and Coverlay.
- New Padstack Editor
A new Padstack Editor has been introduced in OrCAD PCB Editor 17.2-2016 to ease padstack creation through a new modern user interface. In addition to supporting new pad geometries, drill types, additional attributes, and additional mask layers ability to define keep-outs within the padstack with complex geometries for all objects, the new capabilities allow PCB librarians to help PCB designers streamline the design process for complex padstacks, and also the commonly used padstacks.
- OrCAD PCB Designer 17.2-2016 Features
The OrCAD PCB Designer 17.2-2016 release also include new features or enhancements targeted towards improving PCB editors’ productivity and ease-of-use. Other new features include: Via2via Line Fattening (HDI), Display Segments Over Voids, Layer Set Based Routing, Diff Pair Routing and DRC, Full Xnet Support, Gloss Commands, Contour Routing, and many more.
- OrCAD Capture Design Difference Viewer
The Graphical Design Difference Viewer is a powerful, real-time, design difference, visual review utility in OrCAD Capture with the ability to perform logical as well as graphical comparisons on a page-by-page basis. The Graphical Design Difference Viewer generates an interactive single-report HTML file that is platform and tool independent, a unique viewing feature to identify the differences leading to changes in circuit behavior as well as differences based on individual object level, thereby helping address the specialized needs of the users.
- Advanced Annotation
With the newly introduced Advanced Annotation feature supported by OrCAD Capture, users can assign reference ranges hierarchically by automatically assigning values and perform annotation on the whole design, on hierarchy block at any level, page and property block, giving them complete control over their component annotation process in the design cycle.
- PSpice Virtual Prototyping
The new virtual prototyping functionality introduced in PSpice helps electrical engineers overcome design challenges by automating the code generation for multi-level abstraction models written in C/C++ and SystemC. This functionality assists them in generating code requiring limited coding capabilities by design engineers and thereby making the process of virtual prototyping extremely convenient and easy.

Note: The ADW product line, individual ADW products, and product family names have been rebranded in release 17.2-2016. The Allegro Design Workbench (ADW) is now referred to as Allegro Engineering Data Management (EDM). For the full list of new and improved features, and fixed bugs please refer to the release notes located here https://icerbox.com/Vn29dRLO/Cadence_SPB_17.2_Release_Notes.pdf

About Hot-Fix. A Hot-Fix enables a customer to receive fixes for urgent problems, without having to wait for the next service pack. Unlike Service Packs (SP), which are scheduled, periodic releases, Hot-Fix releases are not periodically scheduled. Simply requesting a Hot-Fix does not automatically guarantee that the customer will receive it: all Hot-Fix requests first must be approved and accepted by Cadence prior to delivery. Furthermore, a Hot-Fix may contain fixes related to problems reported earlier by different customers. All the files included in the Hot-Fix will nevertheless be installed.

About Cadence. Cadence enables global electronic design innovation and plays an essential role in the creation of today’s integrated circuits and electronics. Customers use Cadence software, hardware, IP and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers and research facilities around the world to serve the global electronics industry.

Product: Cadence Allegro and OrCAD (Including EDM)
Version: 17.20.000-2016 HF033
Supported Architectures: x64
Language: english
System Requirements: PC
Supported Operating Systems: Windows 7even or newer / 2008 Server R2 / 2012 Server
System Requirements: Cadence Allegro and OrCAD (Including EDM) version 17.20.000-2016 and above


Download File Size:2.6 GB

Cadence Allegro and OrCAD 17.20.000-2016 HF033 x64
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